Description
With the "Detect positive signal edge" instruction, you can detect a state change from "0" to "1" at the CLK input. The instruction compares the current value at the CLK input with the state of the previous query (edge memory bit) that is saved in the specified instance. If the instruction detects a state change at the CLK input from "0" to "1", a positive signal edge is generated at the Q output, i.e., the output has the value TRUE or "1" for exactly one cycle.
In all other cases, the signal state at the output of the instruction is "0".
Parameters
The following table shows the parameters of the "Detect positive signal edge" instruction:
|
Parameters |
Declaration |
Data type |
Memory area |
Description |
|
|---|---|---|---|---|---|
|
S7-1200 |
S7-1500 |
||||
|
EN |
Input |
BOOL |
I, Q, M, D, L or constant |
I, Q, M, D, L, T, C or constant |
Enable input |
|
ENO |
Output |
BOOL |
I, Q, M, D, L |
I, Q, M, D, L |
Enable output |
|
CLK |
Input |
BOOL |
I, Q, M, D, L or constant |
I, Q, M, D, L, T, C or constant |
Incoming signal, the edge of which is to be queried. |
|
Q |
Output |
BOOL |
I, Q, M, D, L |
I, Q, M, D, L |
Result of edge evaluation |
Example
The following example shows how the instruction works:
The previous state of the tag at the CLK input is stored in the "R_TRIG_DB" tag. If a change in the signal state from "0" to "1" is detected in the "TagIn_1" and "TagIn_2" operands or in the "TagIn_3" operand, the "TagOut_Q" output has signal state "1" for one cycle.