P_TRIG: Scan RLO for positive signal edge (S7-1200, S7-1500) - STEP 7

FBD (S7-1200, S7-1500)

ft:publication_title
FBD (S7-1200, S7-1500)
Product
STEP 7
Version
V20
Publication date
11/2024
Language
en-US
P_TRIG: Scan RLO for positive signal edge

Description

Use the instruction "Scan RLO for positive signal edge" to query a "0" to "1" change in the signal state of the result of logic operation (RLO). The instruction compares the current signal state of the RLO with the signal state of the previous query, which is saved in an edge memory bit (<operand>). If the instruction detects a change in the RLO from "0" to "1", there is a positive signal edge.

The positive signal edge is queried each time the instruction executes. As soon as a positive single edge is detected, the output Q of the instruction returns the signal state "1" for the length of a program cycle. In all other cases, the output returns the signal state "0".

Note

Modification of the address of the edge memory bit

The address of the edge memory bit must not be used more than once in the program, otherwise the bit memory is overwritten. This would influence edge evaluation and the result would no longer be unequivocal. The memory area of the edge memory bit has to be located in a DB (static area for FB) or in the bit memory area.

Parameters

The following table shows the parameters of the instruction "Scan RLO for positive signal edge":

Parameter

Declaration

Data type

Memory area

Description

CLK

Input

BOOL

I, Q, M, D, L

Current RLO

<Operand>

InOut

BOOL

M, D

Edge memory bit in which the RLO of the previous query is saved.

Q

Output

BOOL

I, Q, M, D, L

Result of edge evaluation

Example

The following example shows how the instruction works:

The RLO of the preceding bit logic operation is saved in the edge memory bit "Tag_M". If a "0" to "1" change is detected in the signal state of the RLO, the program jumps to jump label CAS1.