&: AND logic operation (S7-1200, S7-1500) - STEP 7

FBD (S7-1200, S7-1500)
ft:publication_title
FBD (S7-1200, S7-1500)
Product
STEP 7
Version
V20
Publication date
11/2024
Language
en-US
&: AND logic operation

Description

You can use the instruction "AND logic operation" to query the signal states of two or more specified operands and evaluate them according to the AND truth table.

If the signal state of all the operands is "1", then the condition is fulfilled and the instruction returns the result "1". If the signal state of one of the operands is "0", then the condition is not fulfilled and the instruction generates the result "0".

Note

Instructions displayed as "inactive" at the operands

Under the following conditions:

  • The instruction "AND logic operation" is interconnected at its inputs with multiple comparator operations (e.g. CMP ==) with the data type String, WString or Variant.

  • The result "FALSE" for the instruction "AND logic operation" is already fulfilled by comparator operations of the same type (data type String, WString or Variant) with the signal state "FALSE".

Result: In online mode, the following comparator operations (data type String, WString or Variant) of the interconnection is shown as "inactive".

Example:

Operand 1: CMP == (data type String) returns the signal state "TRUE". CMP == is shown as "active".

Operand 2: CMP == (data type INT) returns the signal state "TRUE". CMP == is shown as "active".

Operand 3: CMP == (data type String) returns the signal state "FALSE". CMP == is shown as "active".

Operand 4: CMP == (data type String) returns the signal state "TRUE". CMP == is shown as "inactive".

Result of the "AND logic operation": Signal state "FALSE".

Parameters

The following table shows the parameters of the instruction "AND logic operation":

Parameters

Declaration

Data type

Memory area

Description

S7-1200

S7-1500

<Operand>

Input

BOOL

I, Q, M, D, L or constant

I, Q, M, D, L, T, C or constant

The operand indicates the bit whose signal state will be queried.

Example

The following example shows how the instruction works:

Output "TagOut" is set, when the signal state of the operands "TagIn_1" and "TagIn_2" is "1" and reset when the state of the operands "TagIn_1" and "TagIn_2" is "0".